The present invention relates generally to semiconductor memory devices, and, more particularly, to NAND flash memory devices and methods of programming the same.
Semiconductor memory devices may be used to store data and read data therefrom. Semiconductor memory devices may be classified into Random Access Memory (RAM) and Read Only Memory (ROM). In RAM devices, the data stored therein is lost when power is turned off. RAM devices include DRAM (Dynamic RAM) and SRAM (Static RAM). ROM devices include PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Devices. Flash memory devices may be classified into two groups: One is a NAND-type flash memory device and the other is a NOR-type flash memory device.
The NAND-type flash memory device includes a word line and a bit line, which are arranged in a matrix format. Memory cells are connected to the word line and the bit line. The word line is selected by a row address, and a bit line is selected by a column address.
The NAND-type flash memory device comprises a large number of memory cells with a string structure. These memory cells are called a “cell array.” A memory cell has a floating gate and a control gate. Electrical erase and program operations are performed by injecting and emitting electric charges to the floating gate. A memory cell in which electric charges are injected in the floating gate is called a “programmed cell,” and a memory cell in which electric charges are emitted from the floating gate is called an “erased cell.”
In a NAND-type flash memory device, the cell array is divided into a plurality of blocks. Each of the blocks comprises a plurality of pages. Each of the pages comprises a plurality of memory cells sharing one word line. The NAND-type flash memory device performs read and write operations by a page unit and performs an erase operation by a block unit.
A NAND-type flash memory device includes a page buffer for temporarily storing data to be stored in the cell array. A mat typically includes one page buffer. One page buffer is typically 2 Kbyte. In this regard, a mat typically includes one cell array and a set of one page buffer.
A conventional programming method for a NAND-type flash memory device includes the following operations: A loading command, an address, and data with respect to the first mat are sequentially input through an I/O line to the NAND-type flash memory device. After data to be programmed, that is, data less than one page quantity is input, the data input to the page buffer is programmed to a cell array of the first mat by a program command at the same time. Next, a program operation with respect to a second mat is performed in the same manner as the program operation with respect to the first mat.
In the conventional programming method of a NAND-type flash memory device, after the program operation with respect to the first mat is completed, an operation for loading data to be programmed in the second mat into the page buffer is performed. According to the conventional program method, it may take a long time to perform the program operation for a plurality of mats.
To reduce a programming time, a NAND-type flash memory device may include a page buffer as well as a cache memory. While a programming operation is performed from the page buffer to the cell array, the cache memory reduces a program time by loading data to be programmed next into the page buffer. However, due to the cache memory, area used for the NAND-type flash memory is increased.